In high speed (e.g., 10 giga bits per second (Gb/s)), high performance, serial communication receivers that require equalization, variable gain amplifiers (VGAs) are sometimes used on the front end of the topology. The VGA is used to either provide gain or attenuation depending on the amplitude of the input signal such that the VGA outputs a substantially constant amplitude signal. The ability to adjust the gain/attenuation of the VGA so that both a very large and very small input voltage swing range at the input to the receiver can be accommodated is desirable for 10 Gb/s serial data communication applications.
Depending on the application, there may be system requirements in which the minimum and maximum input swing range at the input to the receiver is very wide. Thus, it can be difficult to design a VGA block capable of covering this wide input dynamic range while still being robust to manufacturing process, power supply (VDD), and temperature variations (hereby designated as PVT). Similarly, it may be possible to design a VGA block capable of covering the entire input dynamic range but at the cost of loss of linearity, or distortion.
Therefore, there is a need for a voltage control circuit for controlling a VGA that accommodates substantially the entire input dynamic range when such dynamic range is very large.